The ACIA is illustrated in figure 3. I am using this ACIA because it is much easier to understand than newer serial interfaces. Once you understand how the . MC Asynchronous Communications Interface Adapter (ACIA) F8DCh CPCI Serial Interface MC Control/Status Register (R/W). Computers transfer data in two ways. Parallel. Serial. Parallel data transfers often 8 or more lines are used to transfer data to a device that is only a few feet away.
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The vast majority of general- purpose microcomputers, except some entirely self- contained portable models, once used a serial interface to communicate with remote peripherals such as CRT terminals.
The serial interface, that moves information from point- to- point one bit at a time, is generally preferred to the parallel interface, that is able to move a group of bits simultaneously. This preference is not due to the high performance of a serial data link, but to its low- cost, simplicity and ease of use.
We first describe how information is transmitted serially and then examine a first- generation parallel- to- serial and serial- to- parallel chip that forms the interface between a microprocessor and a serial data link. Finally, we look at a more modern high- performance serial interface. Note that the serial interface is rarely used in new equipment having been rendered obsolete by USB.
However, we have included it here because of its importance and its continued use in legacy systems. Figure 1 illustrates the basic serial data link between a computer and a CRT terminal. A CRT terminal requires a two- way data link, because information from the keyboard is acix to the computer and information from the computer is transmitted to the screen.
The transmitted data from the computer becomes the received data at the CRT terminal. The heart of the data link is the box labeled serial interface that translates data between the form in which it is stored within the computer and the form in which it is transmitted over the data link.
This function is often performed by a single device called an asynchronous communications interface adaptor ACIA. The line drivers in figure 1 translate the voltage levels processed by the ACIA into a suitable form for sending over the transmission path.
The transmission path itself is normally a twisted pair of conductors which accounts for its very low cost. Some systems employ more esoteric transmission paths such as fiber optics, or infra- red IR links. The connection between the line drivers and transmission path is labeled plug and socket in figure 1 to emphasize that such mundane things as plugs become very important if interchangeability is required. International specifications cover this and other aspects of the data link. The two items at the computer end of the data link enclosed in clouds in figure 1 represent the software components of the data link.
The lower cloud contains the software that directly controls the serial interface itself. This software performs operations such as transmitting a single character, or receiving a character and checking it for certain types of error. On top of this layer sits the application- level software, that uses the primitive operations executed by the lower- level software to carry out actions such as listing a file on the screen.
Here we introduce the chip that converts information between the parallel form in which it is processed by the computer and the form in which it is transmitted over the data link. A serial data link operates in one of two modes: We describe only the asynchronous data link because synchronous serial data links are best left to texts on networks. The term character refers to the basic unit of information transmitted over an asynchronous data link.
Many data links transmit information in the form of text and the unit of information corresponds to a printed character. Until the introduction of USB the most popular serial interface between a computer and its CRT terminal is the asynchronous serial interface.
It is so called because the transmitted data and the received data are not synchronized over any extended period and therefore no special means of synchronizing the clocks at the transmitter and receiver is necessary. In fact, the asynchronous serial data link is a very old form of data transmission system and has its origin in the era of the teleprinter. Serial data transmission systems have been around for a long time and are found in the telephone human speechMorse code, semaphore and even the smoke signals once used by Native Americans.
The fundamental problem encountered by all serial data transmission systems is how to split the incoming data- stream into individual units i. For example, in Morse code the dots and dashes of a character are separated by an inter- symbol space, whereas the individual characters are separated by an inter- character space which is three times the duration of an inter- symbol space. First we examine how the data stream is divided into individual bits and the bits grouped into characters in an asynchronous serial data link.
The key to the operation of this type of link is both simple and ingenious. An asynchronous serial data link is character orientedbecause information is transmitted in the form of groups of bits called characters. These characters are invariably units comprising seven or eight bits of information plus two to four control bits.
Initially, when no information is being transmitted, the line is in an idle state. Traditionally, the idle state is referred to as the mark level, which, by convention, corresponds to a logical one level. When the transmitter wishes to send data, it first places the line in a space level i.
This element is called the start bit and has a duration of T seconds. The transmitter then sends the character, one bit at a time, by placing each successive bit on the line for a duration of T seconds, until all bits have been transmitted. After this has been done, a single parity bit is calculated by the transmitter and sent after the data bits.
Finally, the transmitter sends a stop bit at a mark level i. Now the transmitter may send another character whenever it wishes. The only purpose of the stop bit is to provide a rest period for the receiver between consecutive characters.
This stop bit is a relic of the days of electromechanical receivers, and is not now strictly required for technical reasons. It is there for the purpose of compatibility with older equipment. As the data word length may be 7 or 8 bits with odd, even, or no parity bit, plus either one or two stop bits, there are a total of 12 different possible formats for serial data transmission.
And this is before we consider that there are about seven commonly used values of T, the element duration. Consequently, connecting one serial link with another may be difficult because so many options are available. At the receiving end of an asynchronous serial data link, the receiver continually monitors the line looking for a start bit. Once the start bit has been detected, the receiver waits until the end of the start bit and then samples the next N bits at their centers, using a clock generated locally by the receiver.
As each incoming bit is sampled, it is used to construct a new character. When the received character has been assembled, its parity is calculated and compared with the received parity bit following the character. If they are not equal, a parity error flag is set to indicate a transmission error. The most obvious disadvantage of asynchronous data transmission is the need for a start, parity and stop bit for each transmitted character. A less obvious disadvantage is due to the character- oriented nature of the data link.
Whenever the data link connects a CRT terminal to a computer few problems arise, as the terminal is itself character- oriented. However, if the data link is being used to, say, dump binary data to a magnetic tape, we run into a difficulty.
6850 ACIA chip
If the data aca arranged as 8- bit bytes with all possible values corresponding to valid data elements, it is difficult but not impossible to embed control characters e. If 7- bit characters are used, pure binary data cannot be transmitted in the form of one character per byte. Two characters are needed to record each byte which is clearly inefficient. One of the first general- purpose interface devices produced by semiconductor manufacturers was the asynchronous communications interface adaptoror ACIA.
This device relieves the system software of all the basic acoa involved in converting data between serial and parallel forms. That is, the ACIA contains almost all the logic necessary to provide an asynchronous data link between a computer and an external system. The ACIA is illustrated in figure 3. I am using this ACIA because it is much easier to understand than newer serial interfaces.
From the designer’s point of view, the ‘s hardware can be subdivided aciz three sections: This material is taken from articles I avia on the 68K microprocessor.
Consequently, we describe its interface to the 68K. The ACIA is a byte- oriented device and can be interfaced to either the ‘s lower- order byte or to its upper- order 6580. Some sections of afia ACIA are reset automatically by an internal power- on- reset circuit. Afterwards, a secondary reset can be performed by software, as we shall describe later.
One of the great advantages of peripherals like the ACIA is that they isolate the CPU from the outside aciaa both physically and logically. The physical isolation means that the engineer who is connecting a peripheral device to a microprocessor system does not have to 68550 about the electrical and timing requirements of the CPU itself.
That is, all the engineer needs to understand about the ACIA is the nature of its transmitter- and receiver- side interfaces. Similarly, the peripheral performs acja logical isolation by hiding afia details of information transfer across it. All the actions necessary to serialize the data and append start, parity and stop bits are carried out automatically i.
Here, only the essential details of the ACIA’s transmitter and receiver sides are presented, because the way in which they function is described more fully when we come to the logical organization of the The peripheral- side interface of the is divided into two entirely separate groups – the receiver group that forms the interface between the ACIA and a source of incoming data, and the transmitter group that forms the interface between the ACIA and the destination for outgoing data.
Incoming and outgoing are used with respect to the ACIA. The nature of these signals is strongly affected by one particular role of the ACIA, its role as an interface between a computer and the public switched telephone network via a modem.
A receiver clock must be provided at the RxCLK input pin by the systems designer.
ACIA chip – CPCWiki
This clock may be either one-sixteen- or sixty- four times the rate at which bits are received at the data input terminal. Many xcia ACIAs include on- chip receiver and transmitter clocks, relieving the system designer of the necessity of providing an additional external oscillator. This input is aciw for use in conjunction with a modem and, when low, indicates to the ACIA that the incoming data is valid. This situation may arise if the level i.
The transmitter side of the ACIA comprises four pins: In most applications of the ACIA, the transmitter and receiver clocks are connected together and a common oscillator used for both transmitter and receiver sides of the ACIA. This output is set or cleared under software control and can be used to switch on any equipment needed to transmit the serial data over the data link. When negated, this input inhibits the transmission of data by the ACIA. The software model of the has four user- accessible registers as defined in table 1.
acia baud rate generator datasheet & applicatoin notes – Datasheet Archive
As there are four registers and yet the ACIA has only a single register select input, RS, a way must be found to distinguish between registers. Two registers are read- only i. This is a perfectly logical, indeed an elegant, thing to do. But I don’t like it. I am perfectly happy to accept read- only registers, but I am suspicious of the write- only variety because it is impossible to verify the contents of a write- only register. Suppose you have a program with a bug that aciz an unintended write to a write- only register.
You cannot detect the change by reading back the contents of the register.